An Approach to Excution of Partial Reconfiguration in Fpga Using Xilinx Planahead

Xilinx PLANAHEAD provides RTL to bitstream hierarchical design flow with new user interface and project management capabilities. Partial reconfiguration (PR) is a technique which optimizes utilization of resources of Static Random Access Memory (SRAM) based FPGA dynamically i.e on the fly configuration. In this paper the authors reconfigures some specific regions during runtime [2]. The tool which is used in this paper is Xilinx PLANAHEAD that is having capabilities to reduce the complexities during runtime reconfigurable system for all VIRTEX field programmable gate array. PR dynamically modified hardware portion of the device function downloading full and partial bit streams. The modules which were used during the experiments have been presynthesized and the netlist files were stored in synth directory. The data directory carried the ucf, busmacro and additional netlist files. In this paper the authors reconfigure some specific region of the FPGA with a new functionality at run time while the remaining areas remain static during this time. The complexities during the runtime can be simplified by a tool called PLANAHEAD which was introduced by XILINX that is able to implement during runtime reconfigurable systems for all VIRTEX field programmable gate array (FPGAs).PLANAHEAD is the first graphical environment for partial reconfiguration which gives the flexibility for reducing the board space, change a design in the field and also reduces the power consumption [1].